The present invention relates to MOS transistors manufactured from a thin silicon on insulator (SOI) layer and more particularly to mesa-type transistors, that is, transistors formed from individual blocks etched in the thin silicon layer.
FIG. 1A shows such a silicon block. block 1 is formed on an isolating substrate 2 and above the silicon block 1 is shown the mask portion 3 which has served to delineate it. Conventionally, insulator 2 is constituted by a silicon oxide layer formed on a silicon wafer and mask layer 3 is constituted by a silicon oxide and silicon nitride or an oxide-nitride-oxide (ONO) sandwich. In FIG. 1A, it is assumed that the silicon block 1 was delineated by anisotropic etching (for example in presence of a fluorine plasma) whereby each block exhibits rectilinear edges and has a parallelepiped shape.
FIG. 1B shows an analogous structure to that of FIG. 1A but wherein etching was made by wet etching with an acid such as potassium hydroxide (KOH).
The approach of FIG. 1A is generally preferred because in that case the size of the silicon block 1 corresponds with a great accuracy to the size of mask 3 whereas, in case of isotropic etching, the block size is not precisely determined. In addition, the use of KOH presents drawbacks associated with the possible presence of potassium residues. However, in case of anisotropic etching, the angle between the upper surface of a block is substantially perpendicular to the edges.
FIG. 2A is a lop view of a MOS transistor obtained from a vertical-edges block at an intermediate manufacturing step, and FIGS. 2B and 2C are section views according to planes BB and CC, respectively, of FIG. 2A. Those figures show a manufacturing step wherein the mask layer 3 has been eliminated, a thin gale oxide layer 5 has been deposited and a polysilicon gate layer 6 has been deposited and then etched according to the desired gate shape. After this step, conventionally, drain and source are implanted, spacers are formed on both sides of the gate, drain and source are implanted again and contacts are formed.
Such a circuit presents several drawbacks.
First, as can be seen in FIG. 2B, considering the gate oxide layer 5, the latter will unavoidably exhibit failures near right angle corners 7, whereby points with a low breakdown voltage occur at the upper mesa angles.
A second drawback is associated to the fact that, when the polysilicon gate 6 is etched, this step is anisotropically carried out for maintaining the size of the mask which has served to determine the gate. As a result, there remains conductive residues 8 visible in FIGS. 2A and 2C at the block periphery. Those residues are liable to cause shortings; to eliminate them, the gate has to be overetched and the mask size is no longer maintained, which constitutes a redhibitory drawback in case sizes smaller than one micrometer are to be achieved.
Thirdly, when a MOS transistor is formed, it is generally desired to overdop (according to a conductivity type inverse to that of the drain-source doping) the block periphery to cancel any parasitic transistor effect along transistor edges Such an overdoping implantation cannot be formed from an abrupt edge block as shown in FIG. 1A. It is then necessary to implement more sophisticated techniques, consisting, after forming mask pads 3 and before etching blocks 1, in implanting the silicon layer and annealing same to obtain a lateral penetration into block edges. After etching, blocks with overdoped edges are obtained. This method presents the drawback of requiring several additional manufacturing steps and to be relatively inaccurate.
All the above mentioned drawbacks of the transistors according to the prior art are due to the use of blocks with right angle edges.